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? semiconductor components industries, llc, 2002 may, 2002 rev. 7 1 publication order number: mc10ep195/d mc10ep195, mc100ep195 3.3v / 5vecl programmable delay chip the mc10/100ep195 is a programmable delay chip (pdc) designed primarily for clock deskewing and timing adjustment. it provides variable delay of a differential necl/pecl input transition. the delay section consists of a programmable matrix of gates and multiplexers as shown in the logic diagram, figure 2. the delay increment of the ep195 has a digitally selectable resolution of about 10 ps and a range of up to 10.2 ns. the required delay is selected by the 10 data select inputs d[0:9] which are latched on chip by a high signal on the latch enable (len) control. the approximate delay values for varying tap numbers correlating to d0 (lsb) through d9 (msb) are shown in table 1 and figure 3. because the ep195 is designed using a chain of multiplexers it has a fixed minimum delay of 2.2 ns. an additional pin d10 is provided for cascading multiple pdcs for increased programmable range. the cascade logic allows full control of multiple pdcs. select input pins d0d10 may be threshold controlled by combinations of interconnects between v ef (pin 7) and v cf (pin 8) for cmos, ecl, or ttl level signals. for cmos input levels, leave v cf and v ef open. for ecl operation, short v cf and v ef (pins 7 and 8). for ttl level operation, connect a 1.5 v supply reference to v cf and leave open v ef pin. the 1.5 v reference voltage to v cf pin can be accomplished by placing a 1.5 k or 500 resistor between v cf and v ee for 3.3 v or 5.0 v power supplies, respectively. the v bb pin, an internally generated voltage supply, is available to this device only. for single-ended input conditions, the unused differential input is connected to v bb as a switching reference voltage. v bb may also rebias ac coupled inputs. when used, decouple v bb and v cc via a 0.01 f capacitor and limit current sourcing or sinking to 0.5 ma. when not used, v bb should be left open. the 100 series contains temperature compensation. ? maximum frequency > 2.5 ghz typical ? programmable range: 2.2 ns to 12.2 ns ? 10 ps increments ? pecl mode operating range: v cc = 3.0 v to 5.5 v with v ee = 0 v ? necl mode operating range: v cc = 0 v with v ee = 3.0 v to 5.5 v ? open input default state ? safety clamp on inputs ? a logic high on the en pin will force q to logic low ? d[0:10] can accept either ecl, cmos, or ttl inputs ? v bb output reference voltage 32 1 mcxxx awlyyww ep195 device package shipping ordering information mc10ep195fa lqfp32 250 units/tray mc10ep195far2 lqfp32 2000 tape & reel lqfp32 fa suffix case 873a marking diagram* xxx = 10 or 100 a = assembly location wl = wafer lot yy = year ww = work week *for additional information, see application note and8002/d mc100ep195fa lqfp32 250 units/tray mc100ep195far2 lqfp32 2000 tape & reel http://onsemi.com
mc10ep195, mc100ep195 http://onsemi.com 2 25 26 27 28 29 30 31 32 15 14 13 12 11 10 9 12345678 24 23 22 21 20 19 18 17 16 warning: all v cc and v ee pins must be externally connected to power supply to guarantee proper operation. pin description pin in*, in * en * ecl input enable function ecl signal input d[0:10]* q, q ecl signal output cmos, ecl, or ttl select inputs len* ecl latch enable setmin*2 ecl minimum delay set setmax* ecl maximum delay set cascade, cascade ecl cascade signal v bb output reference voltage v cc positive supply v ee negative supply v cf cmos, ecl, or ttl input select v ef ecl reference mode connection v ee d0 v cc qq nc v cc v cc cascade en setmax v cc v ee len d2 d1 cascade setmin v bb in v ee d8 v ef d3 d4 d5 d6 d7 d9 d10 in v cf nc no connect mc10ep195 mc100ep195 2 setmin will override setmax if both are high. figure 1. 32lead lqfp pinout (top view) * pins will default low when left open. truth table en l q = in en h q logic low len l pass through d[0:10] len h latch d[0:10] setmin l normal mode setmin h min delay path setmax l normal mode setmax h max delay path v cf v ef pin*** ecl mode v cf no connect cmos mode v cf 1.5 v ttl mode** ** for ttl mode, connect appropriate resistor between v cf and v ee pin. *** short v cf (pin 8) and v ef (pin 7). resistor value power supply 1.5 k 3.3 v 500 5.0 v data input operating voltage table power supply data select inputs (d [0:10]) supply (v cc , v ee ) cmos ttl pecl necl pecl n/a necl n/a n/a n/a
d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 in in 512 gd* 0 1 256 gd* 0 1 128 gd* 0 1 64 gd* 0 1 32 gd* 0 1 16 gd* 0 1 8 gd* 0 1 4 gd* 0 1 2 gd* 0 1 1 gd* 0 1 1 gd* 0 1 1 gd* 0 1 latch cascade cascade q q en md** len set min set max 10 bit latch d10 *gd = (gate delay) 10 ps delay per gate **md = (fixed minimum delay) 200 ps delay per multiplexer (total fixed delay approx. 2.2 ns) v bb v cf v ef figure 2. logic diagram v ee mc10ep195, mc100ep195 http://onsemi.com 3 table 1. theoretical delay values d10 d(9:0) value delay value comment 0000000000 0 ps (set min) 0000000001 10 ps 0000000010 20 ps 0000000011 30 ps 0000000100 40 ps 0000000101 50 ps 0000000110 60 ps 0000000111 70 ps 0000001000 80 ps 0000010000 160 ps 0000100000 320 ps 0001000000 640 ps 0010000000 1280 ps 0100000000 2560 ps 1000000000 5120 ps 1111111111 10230 ps 1 xxxxxxxxxx 10240 ps (set max)
mc10ep195, mc100ep195 http://onsemi.com 4 0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10000 11000 12000 13000 14000 0 100 200 300 400 500 600 700 800 900 1000 delay ( ps) decimal value of select inputs (d[9:0]) 85 c 25 c 40 c v cc = 0 v v ee = 3.3 v figure 3. measured delay vs. select inputs attributes characteristics value internal input pulldown resistor 75 k internal input pullup resistor n/a esd protection human body model machine model charged device model > 2 kv > 100 v > 2 kv moisture sensitivity (note 1) level 2 flammability rating oxygen index ul94 code v0 a 1/8 28 to 34 transistor count 1217 devices meets or exceeds jedec spec eia/jesd78 ic latchup test 1. for additional information, see application note and8003/d.
mc10ep195, mc100ep195 http://onsemi.com 5 maximum ratings (note 2) symbol parameter condition 1 condition 2 rating units v cc pecl mode power supply v ee = 0 v 6 v v ee necl mode power supply v cc = 0 v 6 v v i pecl mode input volta g e v ee = 0 v v i v cc 6 v v i pecl mode in ut voltage necl mode input voltage v ee = 0 v v cc = 0 v v i ? ?? ? ? v ee 6 6 v v i out output current continuous surge 50 100 ma ma i bb v bb sink/source 0.5 ma ta operating temperature range 40 to +85 c t stg storage temperature range 65 to +150 c q ja thermal resistance (junctiontoambient) 0 lfpm 500 lfpm 32 lqfp 32 lqfp 80 55 c/w c/w q jc thermal resistance (junctiontocase) std bd 32 lqfp 12 to 17 c/w t sol wave solder < 2 to 3 sec @ 248 c 265 c 2. maximum ratings are those values beyond which device damage may occur. 10ep dc characteristics, pecl v cc = 3.3 v, v ee = 0 v (note 3) 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 110 145 175 120 150 180 120 150 180 ma v oh output high voltage (note 4) 2165 2290 2415 2230 2355 2480 2290 2415 2540 mv v ol output low voltage (note 4) 1365 1490 1615 1430 1555 1680 1490 1615 1740 mv v ih input high voltage (singleended) pecl cmos ttl 2090 2415 2155 1815 2000 2480 2215 2540 mv v il input low voltage (singleended) pecl cmos ttl 1365 1690 1430 1755 1485 400 1490 1815 mv v bb output voltage reference 1790 1890 1990 1855 1955 2055 1915 2015 2115 mv v cf input select 1610 1710 1810 1620 1718 1820 1625 1725 1825 mv v ef mode connection 1920 2020 2120 1980 2080 2180 2030 2130 2230 mv v ihcmr input high voltage common mode range (differential) (note 5) 2.0 3.3 2.0 3.3 2.0 3.3 v i ih input high current 150 150 150 m a i il input low current in in 0.5 150 0.5 150 0.5 150 m a note: ep circuits are designed to meet the dc specifications shown in the above table after thermal equilibrium has been establi shed. the circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 3. input and output parameters vary 1:1 with v cc . v ee can vary +0.3 v to 2.2 v. 4. all loading with 50 w to v cc 2.0 volts. 5. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif ferential input signal.
mc10ep195, mc100ep195 http://onsemi.com 6 10ep dc characteristics, pecl v cc = 5.0 v, v ee = 0 v (note 6) 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current (note 7) 110 145 175 120 150 180 120 150 180 ma v oh output high voltage (note 8) 3865 3990 4115 3930 4055 4180 3990 4115 4240 mv v ol output low voltage (note 8) 3065 3190 3315 3130 3255 3380 3190 3315 3440 mv v ih input high voltage (singleended) pecl cmos ttl 3790 4115 3855 2750 2000 4180 3915 4240 mv v il input low voltage (singleended) pecl cmos ttl 3065 3390 3130 3455 2250 400 3190 3515 mv v bb output voltage reference 3490 3590 3690 3555 3655 3755 3615 3715 3815 mv v cf input select tbd mv v ef mode connection tbd mv v ihcmr input high voltage common mode range (differential) (note 9) 2.0 5.0 2.0 5.0 2.0 5.0 v i ih input high current 150 150 150 m a i il input low current in in 0.5 150 0.5 150 0.5 150 m a note: ep circuits are designed to meet the dc specifications shown in the above table after thermal equilibrium has been establi shed. the circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 6. input and output parameters vary 1:1 with v cc . v ee can vary +2.0 v to 0.5 v. 7. required 500 lfpm air flow when using +5 v power supply. for (v cc v ee ) > 3.3 v, 5 to 10 in line with v ee required for maximum thermal protection at elevated temperatures. recommend v cc v ee operation at 3.8 v. 8. all loading with 50 w to v cc 2.0 volts. 9. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif ferential input signal. 10ep dc characteristics, necl v cc = 0 v, v ee = 5.5 v to 3.0 v (note 10) 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current (note 11) 110 145 175 120 150 180 120 150 180 ma v oh output high voltage (note 12) 1135 1010 885 1070 945 820 1010 885 760 mv v ol output low voltage (note 12) 1935 1810 1685 1870 1745 1620 1810 1685 1560 mv v ih input high voltage (singleended) necl 1210 885 1145 820 1085 760 mv v il input low voltage (singleended) necl 1935 1610 1870 1545 1810 1485 mv v bb output voltage reference 1510 1410 1310 1445 1345 1245 1385 1285 1185 mv v cf input select tbd mv v ef mode connection tbd mv v ihcmr input high voltage common mode range (differential) (note 13) v ee +2.0 0.0 v ee +2.0 0.0 v ee +2.0 0.0 v i ih input high current 150 150 150 m a i il input low current in in 0.5 150 0.5 150 0.5 150 m a note: ep circuits are designed to meet the dc specifications shown in the above table after thermal equilibrium has been establi shed. the circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 10. input and output parameters vary 1:1 with v cc . 11. required 500 lfpm air flow when using +5 v power supply. for (v cc v ee ) > 3.3 v, 5 to 10 in line with v ee required for maximum thermal protection at elevated temperatures. recommend v cc v ee operation at 3.8 v. 12. all loading with 50 w to v cc 2.0 volts. 13. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif ferential input signal.
mc10ep195, mc100ep195 http://onsemi.com 7 100ep dc characteristics, pecl v cc = 3.3 v, v ee = 0 v (note 14) 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 100 135 160 110 140 170 110 145 175 ma v oh output high voltage (note 15) 2155 2280 2405 2155 2280 2405 2155 2280 2405 mv v ol output low voltage (note 15) 1355 1480 1605 1355 1480 1605 1355 1480 1605 mv v ih input high voltage (singleended) pecl cmos ttl 2075 2420 2075 1815 2000 2420 2075 2420 mv v il input low voltage (singleended) pecl cmos ttl 1355 1675 1490 1675 1485 400 1490 1675 mv v bb output voltage reference 1775 1875 1975 1775 1875 1975 1775 1875 1975 mv v cf input select 1610 1720 1825 1610 1720 1825 1610 1720 1825 mv v ef mode connection 1900 2000 2100 1900 2000 2100 1900 2000 2100 mv v ihcmr input high voltage common mode range (differential) (note 16) 2.0 3.3 2.0 3.3 2.0 3.3 v i ih input high current 150 150 150 m a i il input low current in in 0.5 150 0.5 150 0.5 150 m a note: ep circuits are designed to meet the dc specifications shown in the above table after thermal equilibrium has been establi shed. the circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 14. input and output parameters vary 1:1 with v cc . v ee can vary +0.3 v to 2.2 v. 15. all loading with 50 w to v cc 2.0 volts. 16. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif ferential input signal. 100ep dc characteristics, pecl v cc = 5.0 v, v ee = 0 v (note 17) 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current (note 18) 100 135 160 110 140 170 110 145 175 ma v oh output high voltage (note 19) 3855 3980 4105 3855 3980 4105 3855 3980 4105 mv v ol output low voltage (note 19) 3055 3180 3305 3055 3180 3305 3055 3180 3305 mv v ih input high voltage (singleended) pecl cmos ttl 3775 4120 3775 2750 2000 4120 3775 4120 mv v il input low voltage (singleended) pecl cmos ttl 3790 3375 3190 3375 2250 400 3190 3375 mv v bb output voltage reference 3475 3575 3675 3475 3575 3675 3475 3575 3675 mv v cf input select tbd mv v ef mode connection tbd mv v ihcmr input high voltage common mode range (differential) (note 20) 2.0 5.0 2.0 5.0 2.0 5.0 v i ih input high current 150 150 150 m a i il input low current in in 0.5 150 0.5 150 0.5 150 m a note: ep circuits are designed to meet the dc specifications shown in the above table after thermal equilibrium has been establi shed. the circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 17. input and output parameters vary 1:1 with v cc . v ee can vary +2.0 v to 0.5 v. 18. required 500 lfpm air flow when using +5 v power supply. for (v cc v ee ) > 3.3 v, 5 to 10 in line with v ee required for maximum thermal protection at elevated temperatures. recommend v cc v ee operation at 3.8 v. 19. all loading with 50 w to v cc 2.0 volts. 20. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif ferential input signal.
mc10ep195, mc100ep195 http://onsemi.com 8 100ep dc characteristics, necl v cc = 0 v, v ee = 5.5 v to 3.0 v (note 21) 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current (note 22) 100 135 160 110 140 170 110 145 175 ma v oh output high voltage (note 23) 1145 1020 895 1145 1020 895 1145 1020 895 mv v ol output low voltage (note 23) 1945 1820 1695 1945 1820 1695 1945 1820 1695 mv v ih input high voltage (singleended) necl 1225 880 1225 880 1225 880 mv v il input low voltage (singleended) necl 1945 1625 1945 1625 1945 1625 mv v bb output voltage reference 1525 1425 1325 1525 1425 1325 1525 1425 1325 mv v cf input select tbd mv v ef mode connection tbd mv v ihcmr input high voltage common mode range (differential) (note 24) v ee +2.0 0.0 v ee +2.0 0.0 v ee +2.0 0.0 v i ih input high current 150 150 150 m a i il input low current in in 0.5 150 0.5 150 0.5 150 m a note: ep circuits are designed to meet the dc specifications shown in the above table after thermal equilibrium has been establi shed. the circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 21. input and output parameters vary 1:1 with v cc . 22. required 500 lfpm air flow when using +5 v power supply. for (v cc v ee ) > 3.3 v, 5 to 10 in line with v ee required for maximum thermal protection at elevated temperatures. recommend v cc v ee operation at 3.8 v. 23. all loading with 50 w to v cc 2.0 volts. 24. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif ferential input signal.
mc10ep195, mc100ep195 http://onsemi.com 9 ac characteristics v cc = 0 v; v ee = 3.0 v to 5.5 v or v cc = 3.0 v to 5.5 v; v ee = 0 v (note 25) 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit f max maximum frequency (see figure 4. f max /jitter) 2.5 2.5 2.5 ghz t plh t phl propagation delay in to q; d(010) = 0 in to q; d(010) = 1023 en to q; d(010) = 0 d0 to cascade 1650 9500 1600 300 2050 11500 2150 420 2450 13500 2600 500 1800 10000 1800 350 2200 12200 2300 450 2600 14000 2800 550 1950 10800 2000 425 2350 13300 2500 525 2750 15800 3000 625 ps t range programmable range t pd (max) t pd (min) 7850 9450 8200 10000 8850 10950 ps d t step delay (note 26) d0 high d1 high d2 high d3 high d4 high d5 high d6 high d7 high d8 high d9 high 13 27 44 90 130 312 590 1100 2250 4500 14 30 47 97 140 335 650 1180 2400 4800 41 100 145 360 690 1300 2650 5300 ps lin linearity tbd t skew duty cycle skew (note 27) t phl t plh tbd ps t s setup time d to len d to in (note 28) en to in (note 29) 200 300 300 0 140 150 200 300 300 0 160 170 200 300 300 0 180 180 ps t h hold time len to d in to en (note 30) 200 400 60 250 200 400 100 280 200 400 80 300 ps t r release time en to in (note 31) set max to len set min to len 400 350 200 275 400 350 tbd 250 200 400 350 300 225 ps t jit cycletocycle jitter (see figure 4. f max /jitter) 0.2 < 1 0.2 < 1 0.2 < 1 ps v pp input voltage swing (differential) 150 800 1200 150 800 1200 150 800 1200 mv t r t f output rise/fall time 2080% (q) 2080% (cascade) 100 100 180 180 250 250 150 150 210 210 300 300 175 175 230 230 325 325 ps 25. measured using a 750 mv source, 50% duty cycle clock source. all loading with 50 w to v cc 2.0 v. 26. specification limits represent the amount of delay added with the assertion of each individual delay control pin. the variou s combinations of asserted delay control inputs will typically realize d0 resolution steps across the specified programmable range. 27. duty cycle skew guaranteed only for differential operation measured from the cross point of the input to the cross point of the output. 28. this setup time defines the amount of time prior to the input signal the delay tap of the device must be set. 29. this setup time is the minimum time that en must be asserted prior to the next transition of in/in to prevent an output response greater than 75 mv to that in/in transition. 30. this hold time is the minimum time that en must remain asserted after a negative going in or positive going in to prevent an output response greater than 75 mv to that in/in transition. 31. this release time is the minimum time that en must be deasserted prior to the next in/in transition to ensure an output response that meets the specified in to q propagation delay and transition times.
mc10ep195, mc100ep195 http://onsemi.com 10 0 100 200 300 400 500 600 700 800 900 0 1000 2000 3000 frequency (mhz) 1 2 3 4 5 6 7 8 9 (jitter) figure 4. f max /jitter v outpp (mv) jitter out ps (rms) cascading multiple ep195s to increase the programmable range of the ep195, internal cascade circuitry has been included. this circuitry allows for the cascading of multiple ep195s without the need for any external gating. furthermore, this capability requires only one more address line per added e195. obviously, cascading multiple programmable delay chips will result in a larger programmable range: however, this increase is at the expense of a longer minimum delay. figure 5 illustrates the interconnect scheme for cascading two ep195s. as can be seen, this scheme can easily be expanded for larger ep195 chains. the d10 input of the ep195 is the cascade control pin. with the interconnect scheme of figure 5 when d10 is asserted, it signals the need for a larger programmable range than is achievable with a single device. the a11 address can be added to generate a cascade output for the next ep195. for a 2device configuration, a11 is not required. v ee d0 v cc q q nc v cc v cc cascade en setmax v cc v ee len d2 d1 cascade setmin v bb in v ee d8 v ef d3 d4 d5 d6 d7 d9 d10 in v cf input output v ee d0 v cc q q nc v cc v cc cascade en setmax v cc v ee len d2 d1 cascade setmin v bb in v ee d8 v ef d3 d4 d5 d6 d7 d9 d10 in v cf ep195 chip #2 ep195 chip #1 address bus a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 need if chip #3 is used figure 5. cascading interconnect architecture an expansion of the latch section of the block diagram is pictured in figure 6. use of this diagram will simplify the explanation of how the cascade circuitry works. when d10 of chip #1 in figure 5 is low the cascade output will also be low while the cascade bar output will be a logical high. in this condition the set min pin of chip #2 will be asserted and thus all of the latches of chip #2 will be reset and the device will be set at its minimum delay. chip #1, on the other hand, will have both set min and set max deasserted so that its delay will be controlled entirely by the address bus a0ea9. if the delay needed is greater than can be achieved with 1023 gate delays
mc10ep195, mc100ep195 http://onsemi.com 11 (1111111111 on the a0ea9 address bus) d10 will be asserted to signal the need to cascade the delay to the next ep195 device. when d10 is asserted, the set min pin of chip #2 will be deasserted and set max pin asserted resulting in the device delay to be the maximum delay. figure 7 shows the delay time of two ep195 chips in cascade. to expand this cascading scheme to more devices, one simply needs to connect the d10 pin from the next chip to the address bus and cascade outputs to the next chip in the same manner as pictured in figure 5. the only addition to the logic is the increase of one line to the address bus for cascade control of the second programmable delay chip. set min set max to select multiplexers bit 0 d0 q0 len set reset bit 1 d1 q1 len set reset bit 2 d2 q2 len set reset bit 3 d3 q3 len set reset bit 4 d4 q4 len set reset bit 5 d5 q5 len set reset bit 6 d6 q6 len set reset bit 7 d7 q7 len set reset bit 8 d8 q8 len set reset bit 9 d9 q9 len set reset figure 6. expansion of the latch section of the ep195 block diagram variable input to chip #1 and setmin for chip #2 input for chip #1 total d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 delay value delay value 0 0 0 0 0 0 0 0 0 0 0 0 ps 4400 ps 0 0 0 0 0 0 0 0 0 0 1 10 ps 4410 ps 0 0 0 0 0 0 0 0 0 1 0 20 ps 4420 ps 0 0 0 0 0 0 0 0 0 1 1 30 ps 4430 ps 0 0 0 0 0 0 0 0 1 0 0 40 ps 4440 ps 0 0 0 0 0 0 0 0 1 0 1 50 ps 4450 ps 0 0 0 0 0 0 0 0 1 1 0 60 ps 4460 ps 0 0 0 0 0 0 0 0 1 1 1 70 ps 4470 ps 0 0 0 0 0 0 0 1 0 0 0 80 ps 4480 ps 0 0 0 0 0 0 1 0 0 0 0 160 ps 4560 ps 0 0 0 0 0 1 0 0 0 0 0 220 ps 4720 ps 0 0 0 0 1 0 0 0 0 0 0 640 ps 5040 ps 0 0 0 1 0 0 0 0 0 0 0 1280 ps 5680 ps 0 0 1 0 0 0 0 0 0 0 0 2560 ps 6960 ps 0 1 0 0 0 0 0 0 0 0 0 5120 ps 9520 ps 0 1 1 1 1 1 1 1 1 1 1 10230 ps 14630 ps variable input to chip #1 and setmax for chip #2 input for chip #1 total d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 delay value delay value 1 0 0 0 0 0 0 0 0 0 0 10240 ps 14640 ps 1 0 0 0 0 0 0 0 0 0 1 10250 ps 14650 ps 1 0 0 0 0 0 0 0 0 1 0 10260 ps 14660 ps 1 0 0 0 0 0 0 0 0 1 1 10270 ps 14670 ps 1 0 0 0 0 0 0 0 1 0 0 10280 ps 14680 ps 1 0 0 0 0 0 0 0 1 0 1 10290 ps 14690 ps 1 0 0 0 0 0 0 0 1 1 0 10300 ps 14700 ps 1 0 0 0 0 0 0 0 1 1 1 10310 ps 14710 ps 1 0 0 0 0 0 0 1 0 0 0 10320 ps 14720 ps 1 0 0 0 0 0 1 0 0 0 0 10400 ps 14800 ps 1 0 0 0 0 1 0 0 0 0 0 10560 ps 14960 ps 1 0 0 0 1 0 0 0 0 0 0 10880 ps 15280 ps 1 0 0 1 0 0 0 0 0 0 0 11520 ps 15920 ps 1 0 1 0 0 0 0 0 0 0 0 12800 ps 17200 ps 1 1 0 0 0 0 0 0 0 0 0 15360 ps 19760 ps 1 1 1 1 1 1 1 1 1 1 1 20470 ps 24870 ps figure 7. delay value of two ep195 cascaded
mc10ep195, mc100ep195 http://onsemi.com 12 multichannel deskewing the most practical application for ep195 is in multiple channel delay matching. slight differences in impedance and cable length can create large timing skews within a highspeed system. to deskew multiple signal channels, each channel can be sent through each ep195 as shown in figure 8. one signal channel can be used as reference and the other ep195s can be used to adjust the delay to eliminate the timing skews. nearly any highspeed system can be finetuned (as small as 10 ps) to reduce the skew to extremely tight tolerances. ep195 in q in q #1 ep195 in q in q #2 ep195 in q in q #n digital data control logic figure 8. multiple channel deskewing diagram measure unknown high speed device delays ep195s provide a possible solution to measure the unknown delay of a device with a high degree of precision. by combining two ep195s and ep31 as shown in figure 9, the delay can be measured. the first ep195 can be set to setmin and its output is used to drive the unknown delay device, which in turn drives the input of a d flipflop of ep31. the second ep195 is triggered along with the first ep195 and its output provides a clock signal for ep31. the programmed delay of the second ep195 is varied to detect the output edge from the unknown delay device. if the programmed delay through the second ep195 is too long, the flipflop output will be at logic high. on the other hand, if the programmed delay through the second ep195 is too short, the flipflop output will be at a logic low. if the programmed delay is correctly finetuned in the second ep195, the flipflop will bounce between logic high and logic low. the digital code in the second ep195 can be directly correlated into an accurate device delay. ep195 in q in q #1 ep195 in q in q #2 unknown delay device control logic d clk q q ep31 clock clock figure 9. multiple channel deskewing diagram
mc10ep195, mc100ep195 http://onsemi.com 13 figure 10. typical termination for output driver and device evaluation (see application note and8020 termination of ecl logic devices.) driver device receiver device d d q q 50 w 50 w v tt v tt = v cc 2.0 v resource reference of application notes an1404 eclinps circuit performance at nonstandard v ih levels an1405 ecl clock distribution techniques an1406 designing with pecl (ecl at +5.0 v) an1504 metastability and the eclinps family an1568 interfacing between lvds and ecl an1650 using wireor ties in eclinps designs an1672 the ecl translator guide and8001 odd number counters design and8002 marking and date codes and8009 eclinps plus spice i/o model kit and8020 termination of ecl logic devices for an updated list of application notes, please see our website at http://onsemi.com.
mc10ep195, mc100ep195 http://onsemi.com 14 package dimensions lqfp fa suffix 32lead plastic package case 873a02 issue a detail y a s1 v b 1 8 9 17 25 32 ae ae p detail y base n j d f metal section aeae g seating plane r q w k x 0.250 (0.010) gauge plane e c h detail ad dim a min max min max inches 7.000 bsc 0.276 bsc millimeters b 7.000 bsc 0.276 bsc c 1.400 1.600 0.055 0.063 d 0.300 0.450 0.012 0.018 e 1.350 1.450 0.053 0.057 f 0.300 0.400 0.012 0.016 g 0.800 bsc 0.031 bsc h 0.050 0.150 0.002 0.006 j 0.090 0.200 0.004 0.008 k 0.500 0.700 0.020 0.028 m 12 ref 12 ref n 0.090 0.160 0.004 0.006 p 0.400 bsc 0.016 bsc q 1 5 1 5 r 0.150 0.250 0.006 0.010 v 9.000 bsc 0.354 bsc v1 4.500 bsc 0.177 bsc detail ad a1 b1 v1 4x s 4x b1 3.500 bsc 0.138 bsc a1 3.500 bsc 0.138 bsc s 9.000 bsc 0.354 bsc s1 4.500 bsc 0.177 bsc w 0.200 ref 0.008 ref x 1.000 ref 0.039 ref 9 t z u t-u 0.20 (0.008) z ac t-u 0.20 (0.008) z ab 0.10 (0.004) ac ac ab m 8x t, u, z t-u m 0.20 (0.008) z ac notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. datum plane -ab- is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4. datums -t-, -u-, and -z- to be determined at datum plane -ab-. 5. dimensions s and v to be determined at seating plane -ac-. 6. dimensions a and b do not include mold protrusion. allowable protrusion is 0.250 (0.010) per side. dimensions a and b do include mold mismatch and are determined at datum plane -ab-. 7. dimension d does not include dambar protrusion. dambar protrusion shall not cause the d dimension to exceed 0.520 (0.020). 8. minimum solder plate thickness shall be 0.0076 (0.0003). 9. exact shape of each corner may vary from depiction.
mc10ep195, mc100ep195 http://onsemi.com 15 notes
mc10ep195, mc100ep195 http://onsemi.com 16 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indem nify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and re asonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized u se, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employ er. publication ordering information japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. mc10ep195/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada

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